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| monochip slic optimised for wll ap- plications implement all key features of the borsht function single supply (5.5 to 15.8v) built in dc/dc converter control- ler. soft battery reversal with pro- grammable transition time. on-hook transmission. programmable off-hook detector threshold metering pulse generation and fil- ter integrated ringing integrated ring trip dual 2w port for data/voice opera- tion parallel control interface (3.3v logic level) programmable constant current feeder surface mount package integrated thermal protection -40 to +85 c operating range description the stlc3065 is a slic device specifically de- signed for wll (wireless local loop) application. one of the distinctive characteristics of this de- vice is the ability to operate with a single supply voltage (from +5.5v to +15.8v) and self generate the negative battery by means of an on chip dc/dc converter controller that drives an external october 1999 ? d0 d1 d2 p1 p2 det det1 det2 rttx cac iltf r d iref rlim rth csvr cvcc vpos bgnd tip1 r ing1 tip2 ring2 vbat agnd tx rx zac1 zac rs zb c ttx1 cttx2 fttx ckttx supervision ttx proc ac proc reference switch line d river c rev in put logic and decoder output logic volt. vcc vss agnd line reg. status and functions clk r sense gate vf dc/dc conv. dc proc vbat block diagram tqfp44 ordering numbers: stlc3065q STLC3065QTR stlc3065 wll subscriber line interface circuit 1/27
mos switch. the self generated battery voltage tracks the line resistance. in this way the power dissipation in- side the device is low enough to allow the use of small smd package (tqfp44). other useful characteristics for application in the wll environment are the integrated ringing gen- erator and the dual two wire port that allows to drive two different terminal equipment whether the transmission is voice or data. when one port is transmitting the other one is idle. the control interface is a parallel type with open drain output and 3.3v logic levels. the metering pulses are generated on chip start- ing from two logic signals (0, 3.3v) one defines the metering pulse frequency and the other the metering pulse duration. an on chip circuit then provides the proper shaping and filtering. metering pulse amplitude and shaping (rising and decay time) can be programmed by external com- ponents. a dedicated cancellation circuit avoid possible codec input saturation due to metering pulse echo. constant current feed can be set from 20ma to 40ma. off-hook detection threshold is programmable from 5ma to 9ma. the device, developed in bcd100ii technology (100v process), operates in the extended tem- perature range and integrates a thermal protec- tion that set the device in power down when tj exceeds 140 c. 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 det1 p2 p1 d1 d0 d2 cttx2 cttx1 ckttx det2 det rttx fttx rx zac1 rs zac zb cac tx vf clk vbat1 crev tip2 tip1 n.c. n.c. n.c. ring1 ring2 vbat bgnd rlim agnd cvcc rsense gate vpos csvr iltf rd iref rth d96tl273b 12 13 14 15 16 pin connection absolute maximum ratings symbol parameter value unit v pos positive supply voltage -0.4 to +17 v a/bgnd agnd to bgnd -1 to +1 v v dig pin d0, d1, d2, p1, p2, det, det1, det2 ckttx -0.4 to 5.5 v t j max. junction temperature 150 c v btot (1) vbtot=|vpos|+|vbat|. (total voltage applied to the device supply pins). 100 v (1) vbat is self generated by the on chip dc/dc converter and can be programmed via rf1 and rf2. rf1 and rf2 shall be selected in order to fulfil the a.m limits (see external components table page 13) description (continued) stlc3065 2/27 thermal data symbol parameter value unit r th j-amb thermal resistance junction to ambient typ. 60 c/w pin description n. name function 25 vpos positive supply input ranging from 5.5v to 15.8v. 34 bgnd battery ground, must be shorted with agnd. 27 agnd analog ground, must be shorted with bgnd. 16 zac ac impedance synthesis. 15 zac1 rx buffer output, the ac impedance is connected from this node to zac. 17 rs protection resistors image (the image resistor is connected from this node to zac). 18 zb balance network for 2 to 4 wire conversion (the balance impedance zb is connected from this node to agnd. za impedance is connected from this node to zac1). 20 tx 4 wire output port (tx output). the signal is referred to agnd. if connected to single supply codec input it must be dc decoupled with proper capacitor. 14 rx 4 wire input port (rx input); 300k w input impedance. this signal is referred to agnd. if connected to single supply codec output it must be dc decoupled with proper capacitor. 19 cac ac feedback input, ac/dc split capacitor (cac). 32 iltf transversal line current image output. 41 tip1 2 wire port #1; tip wire (ia is the current sourced from this pin). 37 ring1 2 wire port #1; ring wire (ib is the current sunk into this pin). 42 tip2 2 wire port #2; tip wire (ia is the current sourced from this pin) 36 ring2 2 wire port #2; ring wire (ib is the current sunk into this pin) 28 rlim constant current feed programming pin (via rlim). rlim should be connected close to this pin and pcb layout should avoid noise injection on this pin. 30 rth off-hook threshold programming pin (via rth). rth should be connected close to this pin and pcb layout should avoid noise injection on this pin. 29 iref internal bias current setting pin. rref should be connected close to this pin and pcb layout should avoid noise injection on this pin. 43 crev reverse polarity transition time control. one proper capacitor connected between this pin and agnd is setting the reverse polarity transition time. this is the same transition time used to shape the otrapezoidal ringingo during ringing injection. 26 cvcc internal positive voltage supply filter. operating range symbol parameter value unit v pos positive supply voltage 5.5 to +15.8 v a/bgnd agnd to bgnd -100 to +100 v v dig pin d0, d1, d2, det, det1, det2, ckttx, p 1 ,p 2 -0.25 to 5.25 v t op ambient operating temperature range -40 to +85 c v bat (1) self generated battery voltage -74 max. v (1) vbat is self generated by the on chip dc/dc converter and can be programmed via rf1 and rf2. rf1 and rf2 shall be selected in order to fulfil the a.m limits (see external components table page 10) stlc3065 3/27 functional description the stlc3065 is a device specifically developed for wll application. it is based on a slic core, on purpose optimised for this application, with the addition of a dc/dc converter controller and a dual port in order to ful- fil the wll requirements. the slic core performs the standard feeding, signalling and transmission functions. it can be set in three different operating modes via the d0, d1, d2 pins of the control logic inter- face (0 to 3.3v logic levels). the loop status is carried out on the det pin (active low).the det pin is an open drain output to allow easy interfac- ing with both 3.3v and 5v logic levels. the three possible slic core operating modes are: power down (pwd) active ringing table 1 shows how to set the different slic core operating modes. table 1. slic core operating modes. d0 d1 d2 operating mode 0 0 x power down 0 1 0 active normal polarity 0 1 1 active reverse polarity 1 1 0 active ttx injection (n.p.) 1 1 1 active ttx injection (r.p.) 1 0 0/1 ring (d2 bit toggles @ fring) n. name function 35 vbat regulated battery voltage self generated by the device via dc/dc converter. must be shorted to vbat1. 23 gate driver for external power mos transistor. 21 vf feedback input for dc/dc converter controller. 22 clk power switch controller clock (typ. 125khz). from version marked stlc3065 a5, this pin can also be connected to cvcc or agnd. when the clk pin is connected to cvcc an internal auto-oscillation is internally generated and it is used instead of the external clock. when the clk pin is connected to agnd, the gate output is disabled. 24 rsense voltage input for current sensing. rsense should be connected close to this pin and vpos pin. the pcb layout should minimize the extra resistance introduced by the copper tracks. 1 d0 control interface: input bit 0. 2 d1 control interface: input bit 1. 3 d2 control interface: input bit 2. 4 p1 control interface: port 1 selection bit 5 p2 control interface: port 2 selection bit 8 det logic interface output of the supervision detector (active low). 6 det1 logic interface output of thr linr port 1 detector (active low) 7 det2 logic interface output of thr linr port 2 detector (active low) 33 csvr battery supply filter capacitor. 12 rttx metering pulse cancellation buffer output. ttx filter network should be connected to this point. if not used should be left open. 13 fttx metering pulse buffer input this signal is sent to the line and used to perform ttx filtering. 10 cttx1 metering burst shaping external capacitor. 11 cttx2 metering burst shaping external capacitor. 9 ckttx metering pulse clock input (12 khz or 16khz square wave). 44 vbat1 frame connection. must be shorted to vbat. 38,39, 40 nc not connected. pin description (continued) stlc3065 4/27 the stlc3065 operating modes will be obtained as combination of the slic core status and the dual port configuration. the dc/dc converter controller is driving an ex- ternal power mos transistor (p-channel) in order to generate the negative battery voltage needed for device operation. the dc/dc converter controller is synchronised with an external clk (125khz typ.). from version marked stlc3065 a5, it can be synchronised to an internal clock generated when the pin clk is connected to cvcc. one sensing resistor in series to vpos supply allows to fix the maximum allowed input peak current. this feature is implemented in order to avoid overload on vpos supply in case of line transient (ex. ring trip detection). the typical value is obtained for a sensing resis- tor equal to 110m w that will guarantee an aver- age current consumption from vpos < 700ma. in on-hook condition the self generated battery voltage is set to a predefined value. this value can be adjusted via one external resis- tor (rf1) and it is typical -50v. when ring mode is selected this value is increased up to -70v typ. once the line goes in off-hook condition the dc/dc converter automatically adjust the gener- ated battery voltage in order to feed the line with a fixed dc current (programmable via rlim) opti- mising in this way the power dissipation. the dual port allows to connect the slic core to one of the two possible 2w ports (tip1/ring1, tip2/ring2). dual port concept one switches array integrated in stlc3065 al- lows to connect the tip and ring output of the slic core to one of the two 2w ports (tip1/ring1 or tip2/ring2). for special condi- tions it is also possible to connect both ports to the slic core.the structure of the switches array is shown in fig.1 and it is controlled via the two logic inputs p1 and p2. depending on the switches configurations each 2w port (tip1/ring1 or tip2/ring2) can be set in four possible conditions: open connected to bgnd and battery via two inte- grated 1.5k w resistors. connected to the slic core connected to an internal 300 m a (min.) current source. depending on the slic core operating modes (defined by d0,d1 and d2) only a subset of these conditions can be programmed. slic core dc/dc converter controller tip1 ring1 ring2 tip2 tx rx control interface sw3t sw5r sw6r sw4t sw1t sw1t sw2r sw2t sw3r 300 m a sw4r 300 m a functional diagram stlc3065 5/27 table 2. dual port control. d0 d1 d2 p1 p2 oper. mode line 1 line 2 det det1 det2 0 0 x 0 0 power down open open - - - 0 0 x 1 1 high z feed. to p.s. via res. to p.s. via res. off-hook line 1+2 off-hook line 1 off-hook line 2 0 0 x 0 1 power down/ high z feed. open to p.s. via res. off-hook line 2 - off-hook line 2 0 0 x 1 0 high z feed. power down to p.s. via res. open off-hook line 1 off-hook line 1 - x 1 x 0 0 active 300 m a bias 300 m a bias - - - x 1 x 1 1 active to buffer to buffer off-hook line 1+2 -- x 1 x 0 1 active 300 m a bias to buffer off-hook line 2 -- x 1 x 1 0 active to buffer 300 m a bias off-hook line 1 -- 1 0 x 0 1 ring 300 m a bias 300 m a bias - - - 1 0 x 1 1 ring to buffer to buffer ring-trip line 1+2 -- 1 0 x 0 1 ring 300 m a bias to buffer ring-trip line 2 -- 1 0 x 1 0 ring to buffer 300 m a bias ring-trip line 1 -- r1 r1 r1 r1 is2 is1 vbat tip1 ring1 tip2 ring2 tip ring bgnd sw1t sw1r sw2t sw2r sw4t sw3t sw4r sw3r line driver sw6r sw5r 300 m a 300 m a r1 = 1500 ohm line1 line2 figure 1. dual port concept. stlc3065 6/27 table 2 shows all the possible combinations be- tween switches configurations and operating modes. a detailed description of each configuration can be found in the ooperating modeso descrip- tion section. operating modes power down (pwd) d0 d1 d2 p1 p2 det det1 det2 0 0 x 0 0 disable disable disable dc characteristic & supervision when this mode is selected both 2w ports (tip1/ring1 and tip2/ring2) are in high imped- ance; all switches sw1 to sw6 are open (see fig.1) the slic core is switched off and the line detec- tors are disabled therefore the off-hook condition cannot be detected. this mode can be selected in emergency condi- tion when it is necessary to cut any current deliv- ered to the line. this mode is also forced by stlc3065 in case of thermal overload (tj > 140 c). in this case the device goes back to the previous status as soon as the junction temperature de- crease under the hysteresis threshold. ac characteristics both the 2w ports (tip1/ring1 and tip2/ring2) are set in high impedance, the tx output buffer is a low impedance output, no ac transmission is possible. high impedance feeding (hi-z) d0 d1 d2 p1 p2 det det1 det2 0 0 x 1 1 off/hk line 1+2 off/hk line 1 off/hk line 2 0 0 x 0 1 off/hk line 2 disable off/hk line 1 0 0 x 1 0 off/hk line 1 off/hk line 1 disable dc characteristic & supervision this operating mode is normally selected when the telephone is in on-hook in order to monitor the line status keeping the power consumption at the minimum. the slic core of stlc3065 is in pwd mode (see fig.1 or functional diagram); the two line series switches (sw1; sw2) are open. de- pending on p1, p2 the 2w ports (tip1/ring1 and tip2/ring2) can be in high impedance or connected to the built in feeding resistors (2x1500 w ) via sw3t and sw5r or sw4t and sw6r. p1 controls tip1/ring1 and p2 controls tip2/ring2 (see fig.1 and table 2). when this mode is selected normally both p1, p2 bits should be set to one. the output voltage in on-hook condition is equal to the self generated battery voltage (-50v typ). when off-hook occurs on 2w port 1 (2) the cur- rent flowing through the ring1(2) wire activates the det1 (2_) detector indicating the line status change. when det1 or det2 are activated also the det become active (low logic level). the off-hook threshold in hi-z mode is the same value programmed in active mode. the dc characteristic in hi-z mode is just equal to the self generated battery with 2x(1500w+rp) where: oopeno: the line port termination is in high impedance. oto p.s. via reso: the tip(n) wire is connected to bgnd through a 1500 w resistor , the ring(n) wire is connected to vbat by a 1500 w resistor. the current flowing in the second resistor is used to detect the off-hook . oto buffero: the tip(n) wire and ring(n) wire are connected to the slic core line driver and the off- hook detection is performed using the slic core supervision circuit that drives the det output. o300 m a biaso: the tip(n) wire is connected to bgnd through a 1500 w resistor , the ring(n) wire is biased by a 300 m a current generator to negative battery (vbat) note: see also appendix c stlc3065 7/27 in series (see fig.2), where rp is the external pro- tection resistance. it should be noted that in case of both ports in hi- z mode and both of them in off-hook condition the power dissipated inside the chip could drive the device in thermal protection. this can be pre- vented via a proper software control that should avoid to keep as a steady condition both lines in off-hook and hi-z mode. typical operation is to set the slic core in active mode as soon as off- hook is detected. ac characteristics the ac impedance shown at the 2w ports (tip1/ring1 and tip2/ring2) is the same as the dc one. depending on the p1, p2 bits the tip1/ring1 and tip2/ring2 ac impedance will be 2x(1500 w + rp) or high impedance. active d0 d1 d2 p1 p2 det det1 det2 x 1 x 0 0 disable disable disable x 1 x 1 1 off/hk line 1+2 disable disable x 1 x 0 1 off/hk line 2 disable disable x 1 x 1 0 off/hk line 1 disable disable dc characteristics & supervision when this mode is selected it is because one connected telephone goes off-hook and the stlc3065 is providing both dc feeding and ac transmission. the slic core is in active mode and normally only one of the two port should be connected to it: p1,p2 = (1,0) or (0,1). (see fig.1 and table 2). the unselected port is anyway dc biased being tip wire connected to bgnd via a 1600w resis- tor and the ring wire connected to a 300ma (min.) current source connected to vbat. it should be noted that since vbat is self gener- ated by the stlc3065 and it is tracking the line voltage depending on the loop resistance con- nected to the selected port its voltage can range typically from -12v to -50v. the unselected port status (on/off hook) cannot be detected. for spe- cial configurations it is also possible to set ac- tive mode with both port selected (p1,p2=1,1) or both unselected (p1,p2=0,0). considering now the selected port, this is con- nected to the slic core. the stlc3065 feeds the line with a constant current fixed by rlim (20ma to 40ma range). the on-hook voltage is typically 40v allowing on-hook transmission; the self generated vbat is -52v typ. if the loop resistance is very high and the line current cannot reach the programmed constant current feed value, the stlc3065 behaves like a 40v voltage source with a series impedance equal to the protection resistors 2xrp(typ. 2x41 w ) plus the line series switches (sw1 or sw2) on re- sistance 2xrsw (typ. 2x9 w ). fig.3 shows the typical dc characteristic in ac- tive mode. the line status (on/off hook) is monitored by the slic core supervision circuit. the off-hook threshold can be programmed via the external resistor rth in the range from 5ma to 9ma. when the line goes in off-hook condition the built in dc/dc converter controller set properly the vbat supply in order to keep the loop current fixed to the programmed value. independently on the programmed constant cur- rent value, the tip and ring buffers have a cur- rent source capability limited to 70ma typ. vbat il vl vbat (-50v) slope: 2x(r1+rp) (r1=1500ohm) 2x(r1+rp) figure 2. dc characteristic in hi-z mode. il ilim vl vbat (-50v) 10v 2rp+2rsw (100ohm typ.) (20 to 40ma) figure 3. dc characteristicin active mode stlc3065 8/27 moreover the power available at vbat is control- led by the dc/dc converter that limits the peak current drawn from the vpos supply. the maxi- mum allowed current peak is set by the rsense resistor and it is typically 900mapk. ac characteristics the slic core provides the standard slic trans- mission functions: input impedance synthesis: can be real or complex and is set by a scaled (x50) external zac impedance. transmit and receive: the ac signal present on the 2w port (tip/ring) is transferred to the tx output with a -6db gain and from the rx in- put to the 2w port with a 0db gain. 2 to 4 wire conversion: the balance imped- ance can be real or complex, the proper can- cellation is obtained by means of two external impedance za and zb. once in active mode (d1=1) the slic core can operate in different states setting properly d0 and d2 control bits (see also table3). d0 d1 d2 operating state 0 1 0 active normal polarity 0 1 1 active reverse polarity 1 1 0 active ttx injection (n.p.) 1 1 1 active ttx injection (r.p.) polarity reversal the d2 bit controls the line polarity, the transition between the two polarities is performed in a osofto way. this means that the tip and ring wire ex- change their polarities following a ramp transition (see fig.4). the transition time is controlled by an external capacitor crev. this capacitor is also setting the shape of the ringing trapezoidal wave- form. when the control pins set battery reversal the line polarity is reversed with a proper transition time set via an external capacitor (crev). metering pulse injection (ttx) the metering pulses circuit consist of a burst shaping generator that gives a square wave shaped and a low pass filter to reduce the har- monic distortion of the output signal. the metering pulse is obtained starting from two logic signals: ckttx: is a square wave at the ttx fre- quency (12 or 16khz) and should be perma- nently applied to the ckttx pin or at least for all the duration of the ttx pulse (including ris- ing and decay phases). d0: enable the ttx generation circuit and de- fine the ttx pulse duration. this two signals are then processed by a dedi- cated circuitry integrated on chip that generate the metering pulse as an amplitude modulated shaped squarewave (sqttx) (see fig.5). both the amplitude and the envelope of the squarewave (sqttx) can be programmed by means of external components. in particular the amplitude is set by the two resistors rlv and the shaping by the capacitor cs. the waveform so generated is then filtered and injected on the line. the low pass filter can be ob- tained using the integrated buffer op1 connected between pin fttx (op1 non inverting input) and rttx (op1 output) (see fig.5) and implementing a osallen and keyo configuration. depending on the external components count it is possible to build an optimised application de- pending on the distortion level required. in par- ticular harmonic distortion levels equal to 13%, 6% and 3% can be obtained respectively with first, second and third order filters (see fig.5). the circuit shown in the oapplication diagramo is related to the simple first order filter. once the shaped and filtered signal is obtained at rttx buffer output it is injected on the tip/ring pins with a +6db gain. it should be noted that this is the nominal condi- tion obtained in presence of ideal ttx echo can- cellation (obtained via proper setting of rttx and cttx). in addition the effective level obtained on the line will depend on the line impedance, the protection resistor value and the series switch (sw1 or sw2) on resistance. in the typical application (ttx line impedance =200 w , rp=41 w , sw1,2 on resistance = 9 w and ideal ttx echo cancellation) the metering pulse level on the line will be 1.33 times the level ap- plied to the rttx pin. gnd tip ring dv/dt set by crev 4v typ. 40v typ on-hook figure 4. tip/ring typical transition from direct to reverse polarity stlc3065 9/27 as already mentioned the metering pulse echo cancellation is obtained by means of two external components (rttx and cttx) that should match the line impedance at the ttx frequency. this simple network has a double effect: synthesise a low output impedance at the tip/ring pins at the ttx frequency. cut the eventual ttx echo that will be trans- ferred from the line to the tx output. ringing d0 d1 d2 p1 p2 det det1 det2 1 0 0/1 @fr 1 1 rtrip line 1+2 disable disable 1 0 0/1 @fr 0 1 rtrip line 2 disable disable 1 0 0/1 @fr 1 0 rtrip line 1 disable disable when this mode is selected stlc3065 self gen- erate an higher negative battery (-70v typ.) in or- der to allow a balanced ringing signal of typically 62vpeak. the slic core is set in ring mode via the control inputs d0 and d1 set respectively to 0 and 1. in this condition both the dc and ac feedback loop are disabled and the slic core line drivers operate as voltage buffers. the ring waveform is obtained toggling the d2 con- trol bit at the desired ring frequency. this bit in fact controls the line polarity (0=direct; 1=reverse). as in the active mode the line voltage transition is performed with a ramp transition, obtaining in this way a trapezoidal balanced ring waveform (see fig.6). the shaping is defined by the crev external capacitor. selecting the proper capacitor value it is possible to get different crest fattor values. the following table shows the crest factor values obtained with a 20hz and 25hz ring frequency and with 1ren. this value are valid either with european or usa specification: crev crest factor @20hz crest factor @25hz 22nf 1.2 1.26 27nf 1.25 1.32 33nf 1.33 not significant (*) (*)distorsion already less than 10%. cttx1 cttx2 cs rlv rlv sqttx burst d0 ckttx shaping generator square wave pulse metering sinusoidal wave pulse metering rttx fttx low pass filter - + op1 cfl r1 r2 c2 c1 required external components vs. filter order. figure 5. metering pulse generation circuit. order cfl r1 c! r2 c2 thd 1 x 13% 2 xxxx6% 3xxxxx3% gnd tip ring dv/dt set by crev 2.5v typ. 65v typ. vbat 2.5v typ. figure 6. tip/ring typical ringing waveform stlc3065 10/27 depending on the p1,p2 control bits the ring waveform can be applied to both 2w ports (tip1/ring1 and tip2/ring2) or to one of the two (see also table2). the ring trip detection is performed sensing the variation of the ac line impedance from on hook (relatively high) to off-hook (low). this particular ring trip method allows to operate without dc off- set superimposed on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given negative battery. it should be noted that such a method is opti- mised for operation on short loop applications and may not operate properly in presence of long loop applications (>500 w ). once ring trip is detected, the det output is acti- vated (logic level low), at this point the card con- troller or a simple logic circuit should stop the d2 toggling in order to effectively disconnect the ring signal and then set the stlc3065 in the proper operating mode (normally active). ring level in presence of more tele- phone in parallel. as already mentioned above the maximum cur- rent that can be drawn from the vpos supply is controlled and limited via the external rsense. this will limit also the power available at the self generated negative battery. if for any reason the ringer load will be too high the self generated battery will drop in order to keep the power consumption to the fixed limit and therefore also the ring voltage level will be re- duced. in the typical application with rsense = 110mw the peak current from vpos is limited to about 900ma, which correspond to an average current of 700ma max. in this condition the stlc3065 can drive up to 3ren with a ring frequency fr=25hz (1ren = 1800 w + 1.0 m f, european standard). in order to drive up to 5ren (1ren= 6930 w + 8mf, us standard) it is necessary to modify the external components as follows: crev = 15nf rd = 2.2 k w power on requirements in order to avoid damage to the device when vpos is first applied it is recommended to keep all the logic inputs to a low logic level (0v) until vpos is > 5.5v. in case this power up sequence cannot be guar- anteed, it's recommended to connect a shottky di- ode (bat46 or equivalent) between vbat and bgnd (see figure 7). layout recommendation a properly designed pcb layout is a basic issue to guarantee a correct behaviour and good noise performances. particular care must be taken on the ground con- nection and in this case the star configuration al- lows surely to avoid possible problems (see appli- cation diagram fig. 8). the ground of the power supply (vpos) has to be connected to the center of the star, let's call this point pgnd. this point should show a resis- tance as low as possible, that means it should be a ground plane. noise sources can be identified in not enough good grounds, not enough low impedance sup- plies and parasitic coupling between pcb tracks and high impedance pins of the device. in particular, to avoid noise problems, layout should prevent any coupling between the dc/dc converter components and analog pins that are referred to agnd (ex: rd, iref, rth, rlim, vf). as a first reccomendation the components cv, l, d1, cvpos, rsense should be kept as close as possible to each other and isolated from the other components. additional improvements can be obtained: decoupling the center of the star from the analog ground of stlc3065 using small chokes. adding a capacitor in the range of 100nf between vpos and agnd in order to filter the switch fre- quency on vpos. bat46 bgnd vbat stlc3065 figure 7. shottky diode connection stlc3065 11/27 external components list in order to properly define the external compo- nents value the following system parameters have to be defined: the ac input impedance shown by the slic at the line terminals ozso to which the return loss measurement is referred. it can be real (typ. 600 w ) or complex. the ac balance impedance, it is the equiva- lent impedance of the line ozlo used for evalu- ation of the trans-hybrid loss performances (2/4 wire conversion). it is usually a complex impedance. the value of the two protection resistors rp in series with the line termination. the line impedance at the ttx frequency ozlttxo. the metering pulse level amplitude measured at line termination ov lottx o. in case of low or- der filtering, v lottx represents the amplitude (vrms) of the fundamental frequency compo- nent. (typ 12 or 16khz). pulse metering envelope rise and decay time constant oto. the slope of the ringing waveform o d v tr/ d t o. the value of the constant current limit current oilimo. the value of the off-hook current threshold oi th o. the value of the ring trip rectified average threshold current oi rth o. the value of the required self generated nega- tive battery ov batr o in ring mode (max value is 70v). this value can be obtained from the de- sired ring peak level +5v. the value of the maximum current peak sunk from vpos oipko. stlc3065 12/27 external components name function formula typ. value rref bias setting current rref = 1.3/ibias ibias = 50 m a 26k w 1% csvr negative battery filter csvr = 1/(2 p ? fp ? 1.8m w ) fp = 50hz 1.5nf 10% 100vl rd ring trip threshold setting resistor rd = 100/i rth 2k w name function formula typ. value crd (6) high frequency noise filter 100nf 10% 15vl q1 dc/dc converter switch p ch. mos transistor rds(on) 1.2 w ,vds = -100v total gate charge=20nc max. with vgs=4.5v and vds=1v id>500ma possible choiches: irf9510 or irf9520 or irf9120 or equivalent d1 dc/dc converter series diode vr > 100v, t rr 50ns smbyw01-200 or equivalent rsense dc/dc converter peak current limiting rsense = 100mv/i pk 110m w @i pk = 900ma l (8) dc/dc converter inductor dc resistance 0.1 w (9) l=125 m h rfp1304pv (manuf.: all inductive) or sumida cdrh125 or equivalent cf1 dc/dc converter feedback loop stability 220pf to 470pf (10) rf1 negative battery programming level 250k w zac rs za zb ccomp tx zac1 zac zb tx control interface d0 d1 d2 p1 p2 bgnd cvcc cac cac iref rref gate vbat q1 rf1 clk crev crev d96tl252e csvr stlc3065 d0 d1 d2 p1 p2 det det det1 det1 det2 det2 iltf rlim rlim rth rth csvr rp tip1 agnd vpos vpos ch rsense d1 rx rx rs cttx2 rttx cs cfl rlv rlv ttx clock cttx cvcc rsense rf2 cv vf l clk rp ring1 rp tip2 rp ring2 tip1 ring1 tip2 ring2 cvpos cf1 vdd rdd rd rd ckttx cttx1 fttx rttx supply gnd bgnd agnd suggested ground lay-out vbat1 cvb crd pgnd figure 8. application diagram. stlc3065 15/27 electrical characteristics test conditions: v pos = 6.0v, agnd = bgnd, normal polarity, t amb =25 c. external components as listed in the otypical valueso column of external components table. note: testing of all parameter is performed at 25 c. characterisation as well as design rules used allow correlation of tested performances at other temperatures. all parameters listed here are met in the oper- ating range: -40 to +85 c. dc characteristics symbol parameter test condition min. typ. max. unit v lohi line voltage il = 0, hi-z (high impedance feeding) t amb = 0 to 85 c 44 50 v v lohi line voltage il = 0, hi-z (high impedance feeding) t amb = -40 to 85 c 42 48 v v loa line voltage il = 0, active t amb = 0 to 85 c 33 40 v v loa line voltage il = 0, active t amb = -40 to 85 c 31 37 v ilim lim. current programming range active mode 20 40 ma ilima lim. current accuracy active mode. rel. to programmed value 20ma to 40ma -10 10 ma rfeed hi feeding resistance hi-z (high impedance feeding) 2.4 3.6 k w zrx rx port input impedance 280 k w ac characteristics l/t long. to transv. (see appendix for test circuit) rp = 41 w , 1% tol., active n. p., r l = 600 w (*) f = 300 to 3400hz 48 50 db t/l transv. to long. (see appendix for test circuit) rp = 41 w , 1% tol., active n. p., r l = 600 w (*) f = 300 to 3400hz 40 45 db t/l transv. to long. (see appendix for test circuit) rp = 41 w , 1% tol., active n. p., r l = 600 w (*) f = 1khz 48 53 db 2wrl 2w return loss 300 to 3400hz, active n. p., r l = 600 w (*) 22 26 db thl trans-hybrid loss 300 to 3400hz, 20log|vrx/vtx|, active n. p., r l = 600 w (*) 30 db ovl 2w overload level at line terminals on ref. imped. active n. p., r l = 600 w (*) 10 dbm txoff tx output offset active n. p., r l = 600 w (*) -150 150 mv g24 transmit gain abs. 0dbm @ 1020hz, active n. p., r l = 600 w (*) -6.4 -5.6 db g42 receive gain abs. 0dbm @ 1020hz, active n. p., r l = 600 w (*) -0.4 0.4 db g24f tx gain variation vs. freq. rel. 1020hz; 0dbm, 300 to 3400hz, active n. p., r l = 600 w (*) -0.12 0.12 db stlc3065 16/27 symbol parameter test condition min. typ. max. unit g42f rx gain variation vs. freq. rel. 1020hz; 0dbm, 300 to 3400hz, active n. p., r l = 600 w (*) -0.12 0.12 db v2wp idle channel noise at line psophometric filtered active n. p., r l = 600 w (*) t amb = 0 to +85 c -73 -68 dbmp v2wp idle channel noise at line psophometric filtered active n. p., r l = 600 w (*) t amb = -40 to +85 c -68 dbmp v4wp idle channel noise at line psophometric filtered active n. p., r l = 600 w (*) t amb = 0 to +85 c -75 -70 dbmp v4wp idle channel noise at line psophometric filtered active n. p., r l = 600 w (*) t amb = -40 to +85 c -75 dbmp thd total harmonic distortion active n. p., r l = 600 w (*) -46 db vttx metering pulse level on line actitive - ttx zl = 200 w fttx = 12khz 200 250 mvrms clkfreq clk operating range -10% 125 10% khz ais insolation between 2-wire ports active, odbm0 @ 1020hz, r l = 600 w -20 db ring vring line voltage ring d2 toggling @ fr = 25hz load = 3ren; crest factor = 1.25 1ren = 1800 w + 1.0 m f t amb = 0 to +85 c 45 49 vrms vring line voltage ring d2 toggling @ fr = 25hz load = 3ren; crest factor = 1.25 1ren = 1800 w + 1.0 m f t amb = -40 to +85 c 44 48 vrms lis insolation between 2-wire ports ring mode on port1 -50 dbmp detectors iofftha off/hook current threshold act. mode, rth = 28.7k w 1% (prog. ith = 9ma) 10.5 ma roftha off/hook loop resistance threshold act. mode, rth = 28.7k w 1% (prog. ith = 9ma) 3.4 k w iontha on/hook current threshold act. mode, rth = 28.7k w 1% (prog. ith = 9ma) 6ma rontha on/hook loop resistance threshold act. mode, rth = 28.7k w 1% (prog. ith = 9ma) 8k w ioffth i off/hook current threshold hi z mode, rth = 28.7k w 1% (prog. ith = 9ma) 10.5 ma roffthi off/hook loop resistance threshold hi z mode, rth = 28.7k w 1% (prog. ith = 9ma) 800 w electrical characteristics (continued) (*) r l : line resistance stlc3065 17/27 symbol parameter test condition min. typ. max. unit ionthi on/hook current threshold hi z mode, rth = 28.7k w 1% (prog. ith = 9ma) 6ma ronthi on/hook loop resistance threshold hi z mode, rth = 28.7k w 1% (prog. ith = 9ma) 8k w irt ring trip detector threshold range ring 20 50 ma irta ring trip detector threshold accuracy ring -15 15 % trtd ring trip detection time ring tbd ms td dialling distortion active -1 1 ms rlrt (1) loop resistance 500 w thal tj for th. alarm activation 160 c digital interface inputs: d0, d1, d2, p1, p2,clk outputs: det, det1, det2 vih in put high voltage 2 v vil input low voltage 0.8 v iih input high current -10 10 m a iil input low current -10 10 m a vol output low voltage iol = 1ma 0.45 v psrr and power consumption psrrc power supply rejection vpos to 2w port vripple = 100mvrms 50 to 4000hz 26 36 db ivpos vpos supply current @ ii = 0 hi-z on-hook active on-hook, ring (line open) 52 93 120 60 115 140 ma ma ma ipk peak current limiting accuracy ring off-hook rsense = 110m w -20% 950 +20% mapk electrical characteristics (continued) (1) rlrt = maximum loop resistance (incl. telephone) for correct ring trip detection. stlc3065 18/27 appendix a stlc3065 test circuits referring to the application diagram shown in fig. 8 of the stlc3065 datasheet and using as external components the typ. values specified in the oexternal componentso table (page 16) find below the proper configuration for each measurement. all measurements requiring dc current termination should be performed using owandel & goltermann dc loop holding circuit gh-1o or equivalent. tip1/tip2 ring1/ring2 rx tx stlc3065 application circuit w&g gh1 zref e vs 1kohm 1kohm 100 m f 100ma dc max zin = 100k 200 to 6khz 600ohm 100 m f figure a1. 2w return loss 2wrl = 20log(|zref + zs|/|zref-zs|) = 20log(e/2vs) tip1/tip2 ring1/ring2 rx tx stlc3065 application circuit w&g gh1 vrx vtx 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz 600ohm figure a2. thl trans hybrid loss thl = 20log|vrx/vtx| stlc3065 19/27 tip1/tip2 ring1/ring2 rx tx stlc3065 application circuit w&g gh1 e vtx 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz 600ohm figure a3. g24 transmit gain g24 = 20log|2vtx/e| tip/1tip2 ring1/ring2 rx tx stlc3065 application circuit w&g gh1 vrx vl 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz 600ohm figure a4. g42 receive gain g42 = 20log|vl/vrx| tip1/tip2 ring1/ring2 rx tx stlc3065 application circuit w&g gh1 vl 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz 600ohm vn vpos ~ figure a5. psrrc power supply rejection vpos to 2w port pssrc = 20log|vn/vl| stlc3065 20/27 tip1/tip2 ring1/ring2 rx tx stlc3065 application circuit w&g gh1 vcm vl 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz 300ohm 100 m f 300ohm 100 m f impedance matching better than 0.1% figure a6. l/t longitudinal to transversal conversion l/t = 20log|vcm/vl| 600ohm tip1/tip2 ring1/ring2 rx tx stlc3065 application circuit vcm w&g gh1 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz 300ohm 100 m f 300ohm 100 m f impedance matching better than 0.1% vrx figure a7. t/l transversal to longitudinal conversion t/l = 20log|vrx/vcm| tip1/tip2 ring1/ring2 rx tx stlc3065 application circuit fttx (12 or 16khz) vlttx 200ohm ckttx figure a8. vttx metering pulse level on line stlc3065 21/27 tip1/tip2 ring1\ring2 rx tx stlc3065 application circuit w&g gh1 vl psophometric filtered 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz 600ohm vtx psophometric filtered figure a9. v2wp and w4wp: idle channel psophometric noise at line and tx. v2wp = 20log|vl/0.774l|; v4wp = 20log|vtx/0.774l| tip1/tip2 ring1/ring2 rx tx stlc3065 application circuit vl 600ohm 600ohm 100 m f 100 m f vais tip2/tip1 ring2/ring1 w&g gh1 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz vrx figure a10. ais isolation between 2 wire ports ais = 20log|vais/vl| stlc3065 22/27 tip1/tip2 ring1/ring2 rx tx stlc3065 application circuit vring (true rms meter) 1800ohm fring (25hz) d2 1 m f 600ohm 100 m f 100 m f vlis (psophometric meter) tip2/tip1 ring2/ring1 figure a11. vring, vlis: ring voltage and port isolation stlc3065 23/27 appendix b stlc3065 overvoltage protection tip1 ring1 ring2 tip2 bgnd vbat rp1 rp2 rp1 rp1 rp1 rp2 rp2 rp2 rp2: fuse or ptc 2x sm4t39rx stlc3065 tip1 ring1 ring2 tip2 figure b1. simplified configuration for indoor overvoltage protection bgnd vbat rp2: fuse or ptc 2x sm4t39rx stlc3065 rp1 rp2 tip1 rp1 rp2 ring1 rp1 rp2 tip2 rp1 rp2 ring2 tip1 ring1 tip2 ring2 lcdp 1511 note: rp2 should guarantee ipeak < 10a: otherwise two lcp1511 maybe used figure b2. standard overloltage protection configuration for k20 compliance stlc3065 24/27 appendix c power down, power down hi-z feeding, hi-z feeding hi-z feeding, power down power down, hi-z feeding line 1 state, line 2 state act off hook, ic feeding ic feeding, act off hook ringing, ringing ringing, ic feeding ic feeding, ringing ic feeding, act on hook act on hook, ic feeding act on hook, act on hook sw routine (*) p1=1 p2=0 p1=p2=1 p1=0, p2=1 tj>tth ring burst line 1, d2=0/1 ring burst line 2, d2=0/1 d0=d1=p1=p2=0 line1off hook line1, off hook line1on hook, p1=1, p2=0 line2off hook line2off hook line2on hook p1=p2=1 p1=p2=1 ring burst line1 and 2, d2=0/1 line1 on hook, ring pause ring pause ring pause ring burst ring burst ring burst ring trip detection line 1 ring trip detection line 2 line2on hook, p1=0, p2=1 line1off hook line1off hook line2 off hook line2 off hook off hook detection ring trip detection figure c1. typical state diagram for the stlc3065 operation note: all state transitions are under the microprocessor control. (*) = when the ringing signal is sent to both lines, the stlc3065 is not able to detect the answering line. to detect the answering line, a sw routine is needed that disables first the line 1 (forcing p1=0) and then the line 2 ( forcing p2=0) so as to detect which line is in off hook condition. the on hook condition is declared when it persists for t>tref. ic feeding state is referred to a constant feeding current applied to the local loop and equal to 300 m a. stlc3065 25/27 stlc3065 26/27 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com stlc3065 27/27 |
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